1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a dynamic random access memory (DRAM) having means for screening out defects of capacitor insulating layers of memory cells.
2. Description of the Related Art
In order to secure reliability of semiconductor devices, screening is commonly performed on the devices before their shipment, the detect potential defects in the devices and remove defective elements. The technique of screening most used is burn-in, which can implement voltage acceleration and temperature acceleration simultaneously. In burn-in screening, devices are operated at a voltage higher than their normal operating voltage and a temperature higher than a normal operating temperature. The devices thereby receive, within a short time, a stress greater than that they may receive in their early failure period under normal operating conditions. Of these devices, those which are most likely to have early failure are screened out before shipment. Thus, the devices that may fail early can be removed effectively, and only the devices which are far less likely to have early failure are delivered to customers.
Burn-in is classified into package burn-in and wafer burn-in. In package burn-in, semiconductor devices are subjected to burn-in after they have been sealed in packages as a final product. In wafer burn-in, semiconductor devices are subjected to burn-in while they are still in wafer form.
With DRAMs having a memory capacity of 1M bits or more, it is common that half of a power-supply voltage (VCC/2) is applied to the plate electrode of each memory cell capacitor during normal operation. More specifically, in a DRAM memory cell MC of FIG. 1, for example, a cell transistor 10 has its gate connected to a word line WL, its drain connected to a bit line BL, and its source connected to one terminal (charge storage node 11a) of a capacitor 11. The other terminal (plate electrode 11b) of the capacitor 11 is connected to VCC/2.
To eliminate the defect of the capacitor insulating layer rapidly during voltage stress testing for package burn-in of such a DRAM, an insulating layer of the capacitor (capacitor insulating layer) needs to be aged. A technique of aging the capacitor insulating layer is disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, No. 5, OCTOBER, 1987, pp. 643-650, "A 4-M bit DRAM with Folded-Bit-Line Adaptive Sidewall-Isolated Capacitor (FASIC) Cell", FIG. 11. In this technique, the capacitor plate electrode is set at a power-supply voltage VCC, thereby aging the capacitor insulating layer.
If the insulating layer begins breaking down, and a small leakage current begins to flow, during voltage stress testing, the voltage at the charge storage node 11a of the capacitor 11 will fall, and the voltage applied to the capacitor insulating layer will also fall because the node 11a is in the floating state. When leakage current starts flowing, the voltage stress across the insulating layer falls to 7 V or less if VCC is, for example 7 V. Consequently, it is no longer possible to break down the capacitor insulating layer completely, though the layer has been broken down to some extent, or a considerably long time is required to break down the insulating layer completely.
However, the capacitor insulating layer, whose defect is limited to leakage of small current, brings about degradation of various types of memory-cell operating margins. (The most significant degradation mode is that of data holding characteristic). In many cases it is difficult to detect memory cells having such a degradation mode by means of a functional test conducted after the voltage stress testing. The less prominent such degradation, the more difficult it is to perform successful detection.
Published Unexamined Japanese Patent Application No. 59-500840 which corresponds to PCT Application U.S. 83/00515, PCT Publication No. WO 83/04109 (Nob. 24, 1983) discloses the technique of mounting a voltage-stress applying pad on a DRAM chip and connecting it to capacitor plate electrodes of all memory cells of a memory cell array in common, and applying a negative voltage (-40 V) to the pad from outside the chip during voltage stress testing for DRAM wafer burn-in. In this technique, the semiconductor substrate and word lines are set at ground potential VSS, whereby the capacitor insulating layers of the memory cells can be screened out efficiently within a short period of time. In this case, however, a burn-in testing device external to the wafer requires a negative power supply for supplying the negative voltage.
For a voltage stress testing for package burn-in or wafer burn-in, it is desirable that an external testing device have no negative power supply and that the gate insulating layers of cell transistors be screened efficiently within a short time, while simultaneously screening the capacitor insulating layers of memory cells.